Architecture and Organization

Architecture and Organization (AR) (12%) For Computer Science Students


    AR1. Digital logic and digital systems [core]
   AR2. Machine level representation of data [core]
   AR3. Assembly level machine organization [core]
   AR4. Memory system organization and architecture [core]
   AR5. Functional organization [core]
   AR6. Multiprocessing and alternative architectures [core]
   
Recommended Books:

1.    Computer Organization & Architecture By William Stallings

2.    Structured Computer Organization by Andrew S. Tanenbaum

The computer lies at the heart of computing. Without it most of the computing disciplines today would be a branch of theoretical mathematics. To be a professional in any field of computing today, one should not regard the computer as just a black box that executes programs by magic. All students of computing should acquire some understanding and appreciation of a computer system's functional components, their characteristics, their performance, and their interactions. There are practical implications as well. Students need to understand computer architecture in order to structure a program so that it runs more efficiently on a real machine. In selecting a system to use, they should to able to understand the tradeoff among various components, such as CPU clock speed vs. memory size.

The learning outcomes specified for these topics correspond primarily to the core and are intended to support programs that elect to require only the minimum 36 hours of computer architecture of their students. For programs that want to teach more than the minimum, the same topics (AR1-AR7) can be treated at a more advanced level by implementing a two-course sequence. For programs that want to cover the elective topics, those topics can be introduced within a two-course sequence and/or be treated in a more comprehensive way in a third course.

AR1. Digital logic and digital systems [2%] [core]
Minimum core coverage time: 6 hours
Topics:

• Overview and history of computer architecture
• Fundamental building blocks (logic gates, flip-flops, counters, registers, PLA)
• Logic expressions, minimization, sum of product forms
• Register transfer notation
• Physical considerations (gate delays, fan-in, fan-out)

Learning objectives:

1. Describe the progression of computer architecture from vacuum tubes to VLSI.
2. Demonstrate an understanding of the basic building blocks and their role in the historical development of computer architecture.
3. Use mathematical expressions to describe the functions of simple combinational and sequential circuits.
4. Design a simple circuit using the fundamental building blocks.

AR2. Machine level representation of data [1%] [core]

Minimum core coverage time: 3 hours
Topics:

• Bits, bytes, and words
• Numeric data representation and number bases
• Fixed- and floating-point systems
• Signed and twos-complement representations
• Representation of nonnumeric data (character codes, graphical data)
• Representation of records and arrays

Learning objectives:

1. Explain the reasons for using different formats to represent numerical data.
2. Explain how negative integers are stored in sign-magnitude and twos-complement representation.
3. Convert numerical data from one format to another.
4. Discuss how fixed-length number representations affect accuracy and precision.
5. Describe the internal representation of nonnumeric data.
6. Describe the internal representation of characters, strings, records, and arrays.

AR3. Assembly level machine organization [3%] [core]

Minimum core coverage time: 9 hours
Topics:

• Basic organization of the von Neumann machine
• Control unit; instruction fetch, decode, and execution
• Instruction sets and types (data manipulation, control, I/O)
• Assembly/machine language programming
• Instruction formats
• Addressing modes
• Subroutine call and return mechanisms
• I/O and interrupts

Learning objectives:

1. Explain the organization of the classical von Neumann machine and its major functional units.
2. Explain how an instruction is executed in a classical von Neumann machine.
3. Summarize how instructions are represented at both the machine level and in the context of a symbolic assembler.
4. Explain different instruction formats, such as addresses per instruction and variable length vs. fixed length formats.
5. Write simple assembly language program segments.
6. Demonstrate how fundamental high-level programming constructs are implemented at the machine-language level.
7. Explain how subroutine calls are handled at the assembly level.
8. Explain the basic concepts of interrupts and I/O operations.

AR4. Memory system organization and architecture [2%] [core]

Minimum core coverage time: 5 hours
Topics:

• Storage systems and their technology
• Coding, data compression, and data integrity
• Memory hierarchy
• Main memory organization and operations
• Latency, cycle time, bandwidth, and interleaving
• Cache memories (address mapping, block size, replacement and store policy)
• Virtual memory (page table, TLB)
• Fault handling and reliability

Learning objectives:

1. Identify the main types of memory technology.
2. Explain the effect of memory latency on running time.
3. Explain the use of memory hierarchy to reduce the effective memory latency.
4. Describe the principles of memory management.
5. Describe the role of cache and virtual memory.
6. Explain the workings of a system with virtual memory management.

AR5. Functional organization [3%] [core]

Minimum core coverage time: 7 hours
Topics:

• Implementation of simple datapaths
• Control unit: hardwired realization vs. microprogrammed realization
• Instruction pipelining
• Introduction to instruction-level parallelism (ILP)

Learning objectives:

1. Compare alternative implementation of datapaths.
2. Discuss the concept of control points and the generation of control signals using hardwired or microprogrammed implementations.
3. Explain basic instruction level parallelism using pipelining and the major hazards that may occur.

AR6. Multiprocessing and alternative architectures [1%] [core]

Minimum core coverage time: 3 hours
Topics:

• Introduction to SIMD, MIMD, VLIW, EPIC
• Systolic architecture
• Interconnection networks (hypercube, shuffle-exchange, mesh, crossbar)
• Shared memory systems
• Cache coherence
• Memory models and memory consistency

Learning objectives:

1. Discuss the concept of parallel processing beyond the classical von Neumann model.
2. Describe alternative architectures such as SIMD, MIMD, and VLIW.
3. Explain the concept of interconnection networks and characterize different approaches.
4. Discuss the special concerns that multiprocessing systems present with respect to memory management and describe how these are addressed.